1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device having a plurality of redundancy input/output lines which is capable of repairing a plurality of defective input/output lines by providing a plurality of redundancy input/output lines.
2. Description of the Conventional Art
The semiconductor memory device having a DRAM(Dynamic Random Access Memory) includes a redundancy circuit for thereby enhancing a yield by changing a defective memory cell with a redundancy cell as an extra-memory cell when there is a defective memory cell. As the redundancy circuit, there are a row redundancy circuit, a column redundancy circuit, an input/output redundancy circuit, etc. Namely, the row, column and input/output circuits including a defective memory cell are substituted with a row, column and input/output circuit. In the case of the merged memory logic semiconductor device, there is a multiplex input/output structure having many input/output bits for increasing the width of the data band. In this memory, there is not a difficulty for using the conventional row redundancy structure. However, when using the conventional redundancy structure, too many redundancy columns are needed for a substitution of one column selection line. For example, if the number of input/output lines is 128, 128 redundancy columns are needed. Therefore, the memory of the conventional multiplex input/output structure uses an input/output redundancy structure instead of the known column redundancy circuit.
FIG. 1 illustrates an input/output redundancy global circuit for a conventional semiconductor device. As shown therein, redundancy global input/output lines red.sub.-- gio0 and red.sub.-- gio1 are connected at both ends of a memory cell array 111, respectively. First fuse circuits 131 and second fuse circuits 141 controlling the redundancy input/output lines red.sub.-- gio0 and red.sub.-- gio1 are connected between input/output detection amplifiers 121 and the memory cell arrays 111. The second fuse circuits 141 each are connected with the global input/output lines gio0 through gion-1, respectively. Each of the two first fuse circuits 131 is connected with both ends of each of the second fuse circuits 141. The first fuse circuits 131 each include one fuse. The second fuse circuits 141 each include two fuses. Therefore, the number of fuses is (2n+2), where n represents the number of input/output lines.
In addition, red.sub.-- giob0 and red.sub.-- giob1 are complementary redundancy global input/output lines receiving signals different from the signal level applied to the global input/output lines gio0.about.gion-1.
The first fuse circuits 131 supply the power voltage Vdd to the second fuse circuits 141 when the internal fuses are connected and supply the ground voltage to the second fuse circuits 141 Vss when the fuses are disconnected. The second fuse circuits 141 connect the global input/output lines gio0.about.gion-1 and the input/output lines io0.about.ion-1 to the initial connection state of the same when the internal fuses are connected. When the internal fuses are disconnected, the leftside or rightside global input/output lines are connected with the input/output lines.
FIGS. 2A and 2B illustrate a state before and after a repair with respect to an input/output line based on a conventional input/output redundancy circuit.
As shown in FIG. 2A, in the leftside, the global input/output line gio3 is defective, and in the rightside, the global input/output line gion-2 is defective. In order to repair the defective global input/output lines gio3 and gion-2, the connection as shown in FIG. 2B is implemented. As shown in FIG. 2B, the leftside fuse connecting the input/output line io3 and the global input/output line gio3 is disconnected. In addition, the input/output line io0 is connected with the redundancy global input/output line red.sub.-- gio0, and the input/output line io1 is connected with the global input/output line gio0, and the input/output line io2 is connected with the global input/output line gio1, and the input/output line io3 is connected with the global input/output line gio2. However, the input/output line io4 is connected with the global input/output line gio4.
In addition, the rightside fuse connecting the input line ion-2 and the global input/output line gion-2 is disconnected. The input/output line ion-1 is connected with the redundancy global input/output line red.sub.-- gio1, and the input/output line ion-2 is connected with the global input/output line gion-1. The input/output line ion-3 is connected with the global input/output line gion-3, and the input/output line ion-4 is connected with the global input/output line gion-4.
In the conventional input/output redundancy structure, it is adapted when less than two redundancy input/output lines are adapted. When more than three redundancy input/output lines are needed, it is impossible to adapt the same.